LPC1767 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'LPC1767' PDF : 79 Pages View PDF
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
11.5 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins[1]
Tamb = −40 °C to +85 °C.[2]
Symbol Parameter
Conditions
fSCL
SCL clock
frequency
Standard-mode
Fast-mode
Fast-mode Plus
tf
fall time
[4][5][6][7] of both SDA and
SCL signals
Standard-mode
Fast-mode
Fast-mode Plus
tLOW
LOW period of
the SCL clock
Standard-mode
Fast-mode
Fast-mode Plus
tHIGH
HIGH period of
the SCL clock
Standard-mode
Fast-mode
Fast-mode Plus
tHD;DAT
data hold time [3][4][8]
Standard-mode
Fast-mode
Fast-mode Plus
tSU;DAT
data set-up
time
[9][10]
Standard-mode
Fast-mode
Fast-mode Plus
Min
Max
0
100
0
400
0
1
-
300
20 + 0.1 × Cb 300
-
120
4.7
-
1.3
-
0.5
-
4.0
-
0.6
-
0.26
-
0
-
0
-
0
-
250
-
100
-
50
-
Unit
kHz
kHz
MHz
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see the I2C-bus specification UM10204). This
maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT =
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
LPC1769_68_67_66_65_64_63
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
© NXP B.V. 2011. All rights reserved.
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