LPC1767 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'LPC1767' PDF : 66 Pages View PDF
NXP Semiconductors
LPC1769/68/67/66/65/64
32-bit ARM Cortex-M3 microcontroller
11.5 I2C-bus
Table 11. Dynamic characteristic: I2C-bus pins (Fast-mode Plus)
Tamb = −40 °C to +85 °C; VDD(3V3) over specified ranges.[1][2][3]
Symbol
Parameter
Conditions
Min
fSCL
SCL clock frequency
-
tf
tSU;DAT
fall time
data set-up time
-
-
50
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] CCLK = PCLK = 20 MHz; I2C-bus interface configured in master mode.
[3] Bus capacitance Cb in pF (50 pF), external pull-up resistance = 218 Ω.
Typ
Max
Unit
-
1
MHz
-
45
ns
-
-
ns
SDA
tf
SCL
P
S
Fig 12. I2C-bus pins clock timing
tSU;DAT
002aae860
11.6 I2S-bus interface (LPC1769/68/67/66/65 only)
Table 12. Dynamic characteristics: I2S-bus interface pins
Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ
common to input and output
tr
rise time
tf
fall time
tWH
pulse width HIGH
[1] -
-
[1] -
-
on pins I2STX_CLK and [1] 0.495 × Tcy(clk) -
I2SRX_CLK
tWL
pulse width LOW
on pins I2STX_CLK and [1] -
-
I2SRX_CLK
Max
Unit
35
ns
35
ns
-
-
0.505 × Tcy(clk) ns
output
tv(Q)
data output valid time
on pin I2STX_SDA;
on pin I2STX_WS
[1] -
[1] -
-
30
ns
-
30
ns
input
tsu(D)
data input set-up time
on pin I2SRX_SDA
[1] 3.5
-
-
ns
th(D)
data input hold time
on pin I2SRX_SDA
[1] 4.0
-
-
ns
[1] CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK⁄4; I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK
signal in the I2S-bus specification.
LPC1769_68_67_66_65_64_4
Product data sheet
Rev. 04 — 1 February 2010
© NXP B.V. 2010. All rights reserved.
48 of 66
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