LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Description
P5[3]
141 G14 G10 98 [11] I I/O
-
-
-
I
I/O
P5[4]
206 C3 C4 143 [3] I; I/O
PU O
-
O
O
JTAG_TDO 2 D3 B1 1
(SWO)
JTAG_TDI 4 C2 C3 3
JTAG_TMS 6
(SWDIO)
JTAG_TRST 8
E3 C2 4
D1 D4 5
JTAG_TCK
(SWDCLK)
10 E2 D2 7
[3] O O
[3] I; I
PU
[3] I; I
PU
[3] I; I
PU
[3] i
I
RESET
35 M2 J1
24 [12] I; I
PU
RSTOUT
29 K3 H2 20 [3] OH O
RTC_ALARM 37 N1 H5 26 [13] OL O
RTCX1
RTCX2
USB_D2
34 K2 J2 23 [14] - I
[15]
36 L2 J3 25 [14] - O
[15]
52 U1 N2 37 [9] - I/O
P5[3] — General purpose digital input/output pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
U4_RXD — Receiver input for USART4.
I2C0_SCL — I2C0 clock input/output (this pin uses a
specialized I2C pad that supports I2C Fast Mode Plus).
P5[4] — General purpose digital input/output pin.
U0_OE — RS-485/EIA-485 output enable signal for UART0.
R — Function reserved.
T3_MAT3 — Match output for Timer 3, channel 3.
U4_TXD — Transmitter output for USART4 (input/output in
smart card mode).
Test Data Out for JTAG interface. Also used as Serial wire trace
output.
Test Data In for JTAG interface.
Test Mode Select for JTAG interface. Also used as Serial wire
debug data input/output.
Test Reset for JTAG interface.
Test Clock for JTAG interface. This clock must be slower than
1/6 of the CPU clock (CCLK) for the JTAG interface to operate.
Also used as serial wire clock.
External reset input with 20 ns glitch filter. A LOW-going pulse
as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor
execution to begin at address 0. This pin also serves as the
debug select input. LOW level selects the JTAG boundary scan.
HIGH level selects the ARM SWD debug mode.
Reset status output. A LOW output on this pin indicates that the
device is in the reset state for any reason. This reflects the
RESET input pin and all internal reset sources.
RTC controlled output. This pin has a low drive strength and is
powered by VBAT. It is driven HIGH when an RTC alarm is
generated.
Input to the RTC 32 kHz ultra-low power oscillator circuit.
Output from the RTC 32 kHz ultra-low power oscillator circuit.
USB port 2 bidirectional D line.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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