LPC178X View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC178X
NXP Semiconductors.
'LPC178X' PDF : 117 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Description
P4[29]
176 B10 B9
122 [3] I; I/O
PU O
I
O
I/O
O
O
O
P4[30]
187 B7 C7 130 [3] I; I/O
PU O
P4[31]
193 A4 E7 134 [3] I; I/O
PU O
P5[0] to P5[4]
I/O
P5[0]
P5[1]
P5[2]
9 F4 E5 6
30 J4 H1 21
117 L14 L12 81
[3] I; I/O
PU I/O
I/O
O
[3] I; I/O
PU I/O
I/O
O
[11] I
I/O
-
-
O
-
I/O
P4[29] — General purpose digital input/output pin.
EMC_BLS3 — LOW active Byte Lane select signal 3.
U3_RXD — Receiver input for UART3.
T2_MAT1 — Match output for Timer 2, channel 1.
I2C2_SCL — I2C2 clock input/output (this pin does not use a
specialized I2C pad).
LCD_VD[7] — LCD data.
LCD_VD[11] — LCD data.
LCD_VD[3] — LCD data.
P4[30] — General purpose digital input/output pin.
EMC_CS0 — LOW active Chip Select 0 signal.
P4[31] — General purpose digital input/output pin.
EMC_CS1 — LOW active Chip Select 1 signal.
Port 5: Port 5 is a 5-bit I/O port with individual direction controls
for each bit. The operation of port 5 pins depends upon the pin
function selected via the pin connect block.
P5[0] — General purpose digital input/output pin.
EMC_A[24] — External memory address line 24.
SSP2_MOSI — Master Out Slave In for SSP2.
T2_MAT2 — Match output for Timer 2, channel 2.
P5[1] — General purpose digital input/output pin.
EMC_A[25] — External memory address line 25.
SSP2_MISO — Master In Slave Out for SSP2.
T2_MAT3 — Match output for Timer 2, channel 3.
P5[2] — General purpose digital input/output pin.
R — Function reserved.
R — Function reserved.
T3_MAT2 — Match output for Timer 3, channel 2.
R — Function reserved.
I2C0_SDA — I2C0 data input/output (this pin uses a specialized
I2C pad that supports I2C Fast Mode Plus).
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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