LPC47B272-MS View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47B272-MS' PDF : 195 Pages View PDF
TABLE 4 – REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
REGISTER
ADDRESS
(Note 1)
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
REGISTER NAME
Receive Buffer Register (Read Only)
REGISTER
SYMBOL
BIT 7
RBR
Data Bit 7
BIT 6
Data Bit 6
BIT 5
Data Bit 5
BIT 4
Data Bit 4
BIT 3
BIT 2
BIT 1
Data Bit 3 Data Bit 2 Data Bit 1
Transmitter Holding Register (Write Only)
THR
Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1
BIT 0
Data Bit 0
(Note 2)
Data Bit 0
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 5)
Divisor Latch (LS)
IER
IIR
FCR
(Note 8)
LCR
MCR
LSR
MSR
SCR
DDL
0
0
FIFOs
Enabled
(Note 6)
RCVR
Trigger
MSB
Divisor
Latch
Access Bit
(DLAB)
0
FIFOs
Enabled
(Note 6)
RCVR
Trigger LSB
Set Break
0
Error in
RCVR FIFO
(Note 6)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Transmitter
Empty
(TEMT)
(Note 3)
Ring
Indicator
(RI)
Bit 6
Bit 6
0
0
Reserved
Stick Parity
0
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
0
0
Reserved
Even Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear to
Send (CTS)
Bit 4
Bit 4
Enable
MODEM
Status
Interrupt
(EMSI)
Interrupt ID
Bit (Note 6)
DMA Mode
Select
(Note 7)
Parity
Enable
(PEN)
OUT2
(Note 4)
Framing
Error (FE)
Delta Data
Carrier
Detect
(DDCD)
Bit 3
Bit 3
Enable
Receiver
Line
Status
Interrupt
(ELSI)
Interrupt
ID Bit
XMIT FIFO
Reset
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
RCVR
FIFO Reset
Enable
Received
Data
Available
Interrupt
(ERDAI)
“0” if
Interrupt
Pending
FIFO Enable
Number of
Stop Bits
(STB)
Word
Length
Select Bit 1
(WLS1)
Word Length
Select Bit 0
(WLS0)
OUT1
(Note 4)
Parity
Error (PE)
Request to
Send (RTS)
Overrun
Error (OE)
Data
Terminal
Ready (DTR)
Data Ready
(DR)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Delta Data
Set Ready
(DDSR)
Bit 1
Bit 1
Delta Clear
to Send
(DCTS)
Bit 0
Bit 0
Divisor Latch (MS)
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SMSC LPC47B27x
- 65 -
Rev. 04-17-07
DATASHEET
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