LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M112-MC
SMSC -> Microchip
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
14us
8042 P20
6us
KRST
KRST_GA20
P92
Bit 2
Bit 0
Pulse
Gen
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
14us
nALT_RST
KBDRST
6us
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible
software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to
control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low
drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92
Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE
from the keyboard controller. Upon reset, this signal is driven low.
21.1 Latches On Keyboard and Mouse IRQs
The implementation of the latches on the keyboard and mouse interrupts is shown below.
SMSC DS – LPC47M112
Page 111
DATASHEET
Rev. 02-16-07
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