LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M112-MC
SMSC -> Microchip
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
Table 11 - FIFO Service Delay
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING AT
2 Mbps DATA RATE
1 x 4 μs - 1.5 μs = 2.5 μs
2 x 4 μs - 1.5 μs = 6.5 μs
8 x 4 μs - 1.5 μs = 30.5 μs
15 x 4 μs - 1.5 μs = 58.5 μs
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING AT
1 Mbps DATA RATE
1 x 8 μs - 1.5 μs = 6.5 μs
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
MAXIMUM DELAY TO SERVICING AT
500 Kbps DATA RATE
1 x 16 μs - 1.5 μs = 14.5 μs
2 x 16 μs - 1.5 μs = 30.5 μs
8 x 16 μs - 1.5 μs = 126.5 μs
15 x 16 μs - 1.5 μs = 238.5 μs
7
6
5
4
3
2
1
0
DSK
0
0
0
0
0
0
0
CHG
RESET N/A N/A N/A N/A N/A N/A N/A N/A
COND.
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
PS/2 Mode
7
6
5
4
3
2
1
0
DSK
1
1
1
1 DRATE DRATE nHIGH
CHG
SEL1 SEL0 nDENS
RESET N/A N/A N/A N/A N/A N/A N/A
1
COND.
SMSC DS – LPC47M112
Page 34
DATASHEET
Rev. 02-16-07
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