LPC47M112 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47M112

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

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Enhanced Super I/O Controller with LPC Interface

Datasheet

FIFO

MODE

ONLY

BIT 3

1

0

0

INTERRUPT

IDENTIFICATION

REGISTER

BIT 2 BIT 1 BIT 0

1

0

0

0

1

0

0

0

0

INTERRUPT SET AND RESET FUNCTIONS

PRIORITY INTERRUPT

LEVEL

TYPE

INTERRUPT

SOURCE

INTERRUPT

RESET

CONTROL

drops below the

trigger level.

Second

Character

Timeout

Indication

No Characters

Have Been

Removed From or

Input to the RCVR

FIFO during the

last 4 Char times

and there is at

least 1 char in it

during this time

Reading the

Receiver Buffer

Register

Third

Transmitter

Transmitter

Holding

Holding Register

Register Empty Empty

Reading the IIR

Register (if Source

of Interrupt) or

Writing the

Transmitter

Holding Register

Fourth

MODEM

Status

Clear to Send or Reading the

Data Set Ready or MODEM Status

Ring Indicator or Register

Data Carrier

Detect

LINE CONTROL REGISTER (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

Start LSB Data 5-8 bits MSB Parity Stop

SMSC DS – LPC47M112

Page 65

DATASHEET

Rev. 02-16-07

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