LPC47M14X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47M14X' PDF : 205 Pages View PDF
LOGICAL
DEVICE
NUMBER
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Table 65 – I/O Base Address Configuration Register Description
BASE I/O
LOGICAL
DEVICE
REGISTER
INDEX
RANGE
(NOTE 1)
FIXED
BASE OFFSETS
FDC
0x60,0x61
[0x0100:0x0FF8]
+0 : SRA
+1 : SRB
ON 8 BYTE BOUNDARIES +2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
Reserved
n/a
n/a
n/a
Reserved
n/a
n/a
n/a
Parallel
0x60,0x61
[0x0100:0x0FFC]
+0 : Data/ecpAfifo
Port
ON 4 BYTE BOUNDARIES +1 : Status
(EPP Not supported)
+2 : Control
or
+400h : cfifo/ecpDfifo/tfifo/cnfgA
[0x0100:0x0FF8]
+401h : cnfgB
ON 8 BYTE BOUNDARIES +402h : ecr
(all modes supported, +3 : EPP Address
EPP is only available when +4 : EPP Data 0
the base address is on an 8- +5 : EPP Data 1
byte boundary)
+6 : EPP Data 2
+7 : EPP Data 3
Serial Port 1 0x60,0x61
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
ON 8 BYTE BOUNDARIES +2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
Serial Port 2 0x60,0x61
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
ON 8 BYTE BOUNDARIES +2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
Reserved
n/a
n/a
n/a
KYBD
n/a
Not Relocatable
+0 : Data Register
Fixed Base Address: 60,64 +4 : Command/Status Reg.
Reserved
n/a
n/a
n/a
Game Port 0x60,0x61
[0x0100:0x0FFF]
+00: Game Port Register
on 1 byte boundaries
Runtime
Register
Block
0x60,0x61
[0x0000:0x0F7F]
on 128-byte boundaries
+00 : PME Status
.
.
.
+5F : Keyboard Scan Code
(See Table in “Runtime Registers”
section for Full List)
SMSC DS – LPC47M14X
Page 161
Rev. 03/19/2001
Share Link: 
