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LPC47M14X View Datasheet(PDF) - SMSC -> Microchip

Part Name
Description
MFG CO.
'LPC47M14X' PDF : 205 Pages View PDF
Table 30 – Interrupt Control Table
FIFO
MODE
ONLY
BIT 3
0
0
0
1
0
0
INTERRUPT
IDENTIFICATION
REGISTER
BIT 2 BIT 1 BIT 0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY INTERRUPT
LEVEL
TYPE
INTERRUPT
SOURCE
INTERRUPT
RESET
CONTROL
-
None
None
-
Highest
Receiver Line
Status
Overrun Error,
Parity Error,
Framing Error or
Break Interrupt
Reading the Line
Status Register
Second
Received Data
Available
Receiver Data
Available
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Second
Character
Timeout
Indication
No Characters
Have Been
Removed From or
Input to the RCVR
FIFO during the
last 4 Char times
and there is at
least 1 char in it
during this time
Reading the
Receiver Buffer
Register
Third
Transmitter
Holding
Register Empty
Transmitter
Holding Register
Empty
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter
Holding Register
Fourth
MODEM
Status
Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier
Detect
Reading the
MODEM Status
Register
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
Serial Data
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1
is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1
0
0
1
1
BIT 0
0
1
0
1
WORD LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
SMSC DS – LPC47M14X
Page 63
Rev. 05/02/2000
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