LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
EPP
SIGNAL
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
EPP NAME
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
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Status
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Table 36 - EPP Pin Descriptions
TYPE
O
I/O
I
I
O
O
O
I
I
EPP DESCRIPTION
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device
is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
I Same as SPP mode.
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.
For correct EPP read cycles, PCD is required to be a low.
Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost
peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use
of adaptive signal timing Peer-to-peer capability.
Vocabulary
The following terms are used in this document:
assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication
Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is
always 8 bits.
1
A high level.
0
A low level.
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
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