LPC47U332 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U332

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

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Note that when the host is sending data to the

FIFO of the FDC, the internal sector count will

be complete when the FDC reads the last byte

from its side of the FIFO. There may be a delay

in the removal of the transfer request signal of

up to the time taken for the FDC to read the last

16 bytes from the FIFO. The host must tolerate

this delay.

Result Phase

The generation of the interrupt determines the

beginning of the result phase. For each of the

commands, a defined set of result bytes must

be read from the FDC before the result phase is

complete. These bytes of data must be read out

for another command to start.

RQM and DIO must both equal "1" before the

result bytes may be read. After all the result

bytes have been read, the RQM and DIO bits

switch to "1" and "0" respectively, and the CB bit

is cleared, indicating that the FDC is ready to

accept the next command.

Command Set/Descriptions

Commands can be written whenever the FDC is

in the command phase. Each command has a

unique set of needed parameters and status

results. The FDC checks to see that the first

byte is a valid command and, if valid, proceeds

with the command. If it is invalid, an interrupt is

issued. The user sends a Sense Interrupt

Status command, which returns an invalid

command error. Refer to Table 19 for

explanations of the various symbols used. Table

20 lists the required parameters and the results

associated with each command that the FDC is

capable of performing.

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