LPC47U332 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47U332
SMSC -> Microchip
'LPC47U332' PDF : 252 Pages View PDF
Table 31 - Drive Control Delays (ms)
HUT
SRT
2M 1M 500K 300K 250K 2M 1M 500K 300K 250K
0 64 128 256 426 512 4
8
16 26.7 32
14
8
16 26.7 32 3.75 7.5 15 25 30
.. ..
..
..
..
..
..
..
..
..
..
E 56 112 224 373 448 0.5
1
2 3.33 4
F 60 120 240 400 480 0.25 0.5
1 1.67 2
2M
00
64
01
0.5
02
1
..
..
7F
63
7F
63.5
HLT
1M
500K
300K
250K
128
256
426
512
1
2
3.3
4
2
4
6.7
8
..
..
..
.
126
252
420
504
127
254
423
508
Configure Default Values:
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
PRETRK - Pre-Compensation Set to Track 0
EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a
read or write command. Defaults to no implied seek.
EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte
basis. Defaults to "1", FIFO disabled. The threshold defaults to "1".
POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single
interrupt is generated after a reset. No polling is performed while the drive head is loaded and the
head unload delay has not expired.
FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is
programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16
bytes.
PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to
track 0. A "00" selects track 0; "FF" selects track 255.
67
Share Link: 