3.3 VOLT OPERATION / 5 VOLT
TOLERANCE
The LPC47U33x is a 3.3 Volt part. It is intended
solely for 3.3V applications. Non-LPC bus pins
are 5V tolerant; that is, the input voltage is 5.5V
max, and the I/O buffer output pads are
backdrive protected.
The LPC interface pins are 3.3 V only. These
signals meet PCI DC specifications for 3.3V
signaling . These pins are:
• LAD[3:0]
• nLFRAME
• nLDRQ
• nLPCPD
The input voltage for all other pins is 5.5V max.
These pins include all non-LPC Bus pins and
the following LPC pins:
• nPCI_RESET
• PCI_CLK
• SER_IRQ
• nIO_PME
POWER FUNCTIONALITY
The LPC47U33x has three power inputs, VCC,
VTR and VREF.
Current Values” subsection. If the LPC47U33x is
not intended to provide wake-up capabilities on
standby current, VTR can be connected to VCC.
The VTR pin generates a VTR Power-on-Reset
signal to initialize these components.
Note: If VTR is to be used for programmable
wake-up events when VCC is removed, VTR must
be at its full minimum potential at least 10 µs
before Vcc begins a power-on cycle. When VTR
and Vcc are fully powered, the potential
difference between the two supplies must not
exceed 500mV.
VREF PIN
The LPC47U33x has a reference voltage pin
input on pin 44 of the part. This reference
voltage can be connected to either a 5V supply
or a 3.3V supply. It is intended to be used for
the game port.
The reference voltage is used in the game port
logic so that the joystick trigger voltage is 2/3
VREF where VREF is either 5V or 3.3V. This is
to preserve joystick compatibility by maintaining
the RC time constant reset trigger voltage of
3.3V (nominal) with VREF=5V (nominal), if
required.
VCC Power
Internal PWRGOOD
The LPC47U33x is a 3.3 volt part. The VCC
supply is 3.3 volts (nominal). See the
“Operational Description” sections and the
“Maximum Current Values” subsection.
VTR Support
The LPC47U33x requires a trickle supply (VTR)
to provide sleep current for the programmable
wake-up events in the PME interface when VCC
is removed. The VTR supply is 3.3 volts
(nominal). See the “Operational Description”
section. The maximum VTR current that is
required depends on the functions that are used
in the part. See the “Trickle Power
Functionality” subsection and the “Maximum
An internal PWRGOOD logical control is
included to minimize the effects of pin-state
uncertainty in the host interface as Vcc cycles on
and off. When the internal PWRGOOD signal is
“1” (active), Vcc > 2.3V, and the LPC47U33x
host interface is active. When the internal
PWRGOOD signal is “0” (inactive), Vcc <= 2.3V,
and the LPC47U33x host interface is inactive;
that is, LPC bus reads and writes will not be
decoded.
The LPC47U33x device pins nIO_PME,
CLOCKI32, KDAT, MDAT, nRI and GPIOs (as
input) are part of the PME interface and remain
active when the internal PWRGOOD signal has
gone inactive, provided VTR is powered.
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