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LS7213R View Datasheet(PDF) - LSI Computer Systems

Part Name
Description
MFG CO.
LS7213R
LSI-CSI
LSI Computer Systems LSI-CSI
'LS7213R' PDF : 5 Pages View PDF
1 2 3 4 5
D3 1
D2 2
D1 3
LATCH
LATCH
RANGE
DECODER
LATCH
RC 10
OSC
TIMER
OUTPUT
DRIVER
13 O U T 1
OUTPUT
DRIVER
12 O U T 2
POR
GENERATOR
A5
LATCH
OSC
9 CAP
B6
FLASHEN 4
LATCH
LATCH
CONTROL LOGIC
11 R E S E T
TRIGGER 8
LATCH
FIGURE 2. LS7213R BLOCK DIAGRAM
+V 14
-V
7
VDD
Vss
TRIG
RESET
OUT1(OST)
OUT1(OND)
OUT1(OFD)
F
C
D
FIGURE 3.
MODE ILLUSTRATION
WITH TRIG, OUT1 AND RESET
OUT1(DLD)
A
B
E
G
H
A. Turn-on delay in OND and DLD modes; Pulse-width in OST mode.
B. Turn-off delay in OFD and DLD modes.
C. Pulse-width extended by re-trigger in OST mode. No effect in
OND and DLD modes because TRIG switches back low before
turn-on delay has timed out.
D. Turn-off delay in OFD mode.
+5V
E. Turn-on delay in OND and DLD modes; pulse-width in OST mode.
F. No effect in OND, OFD and DLD modes because of Trig’s
switching back to opposite levels.
G. Time-out aborted and OUT1 forced high by RESET.
H. After the removal of RESET, OUT1 switches to the inverse polarity
of TRIG immediately (OFD) or after the timeout (OND, DLD).
No effect in OST.
1 D3
2
D2
V DD (+V) 14
13
OUT1
3
D1
12
OUT2
11
4
RESET
FLASHEN
10
RC
5
A
LS7213R
9
6
CAP
B
7
Vss (-V)
8
TRIGGER
C1
TRIGGER INPUT
RESET INPUT
FIGURE 4. TYPICAL APPLICATION WITH OUT1 AS
RELAY DRIVE AND OUT2 AS FLASHER
7213R-120205-4
R2
R1
300
LED
C2
The table below shows the delays obtained with the
following components R1 = 56k, R2 = 500kand
C2 = 0.002µF. At any scale factor, the delay changes
from minimum to maximum as the potentiometer, R2
is varied from minimum to maximum.
D3 D2 D1
000
001
010
011
100
101
110
111
TIMING RANGE
0.1 sec - 1 sec.
1 sec. - 10 sec.
10 sec - 100 sec.
0.1 min. to 1 min.
1 min. - 10 min
10 min. - 100 min.
0.1 hr. - 1 hr.
1 hr. - 10 hr.
C1 = 0.22µF, produces flash pulses of 0.1 sec
duration at Out2
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