LT1339C View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT1339C' PDF : 20 Pages View PDF
LT1339
W
FUNCTIONAL BLOCK DIAGRA
VIN
VBOOST
PHASE
CT
MAIN
SWITCH
TG
TS
BG
SYNC
SWITCH
SL/ADJ
NONOVERLAPPING
SWITCH LOGIC
UVLO
CIRCUIT
VOUT
RSENSE
+
SENSE+
SENSE–
0.5µA
+
× 15
–
CURRENT
SENSE AMP
VFB
–
EA
VREF
+
5VREF
1.25V
5V
REFERENCE
8µA
SOFT START
RUN/SHDN
+
1.25V –
CIRCUIT
ENABLE
SGND PGND
SS
5VREF
12VIN
OSC
ONE SHOT
Q
S
R
+
IC1
–
SYNC
VC
2.5V –
50k
+
AVERAGE
CURRENT
LIMIT
IAVG
1339 • BD
U
OPERATION (Refer to Functional Block Diagram)
Basic Control Loop
The LT1339 uses a constant frequency, current mode
synchronous architecture. The timing of the IC is provided
through an internal oscillator circuit, which can be syn-
chronized to an external clock, programmable to operate
at frequencies up to 150kHz. The oscillator creates a
modified sawtooth wave at its timing node (CT) with a slow
charge, rapid discharge characteristic.
During typical positive buck operation, the main switch
MOSFET is enabled at the start of each oscillator cycle. The
main switch stays enabled until the current through the
switched inductor, sensed via the voltage across a series
sense resistor (RSENSE), is sufficient to trip the current
comparator (IC1) and, in turn, reset the RS latch. When the
RS latch resets, the main switch is disabled, and the
synchronous switch MOSFET is enabled. Shoot-through
prevention logic prohibits enabling of the synchronous
switch until the main switch is fully disabled. If the current
comparator threshold is not obtained throughout the
entire oscillator charge period, the RS latch is bypassed
and the main switch is disabled during the oscillator
discharge time. This “minimum off time” assures ad-
equate charging of the bootstrap supply, protects the main
switch, and is typically about 1µs.
8
Share Link: 
