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LT1394C View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
'LT1394C' PDF : 16 Pages View PDF
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LT1394
APPLICATIONS INFORMATION
0.1µF
5V
LT1634
DELAY PROGRAMMING
VOLTAGE INPUT
0V TO 3V = 0 TO 300ns DELAY
100
1k
100
(DELAY
CALIB)
51pF
0.1µF
Q1
Q2 Q4
1000pF
Q3
220
PNP = 2N5087
NPN = 2N2369
330
330
LT1394
+
TRIGGER INPUT
200ns MINIMUM
Q OUTPUT
Q OUTPUT
1394 F11
Figure 11. Fast, Precise, Voltage-Controlled Delay.
Emitter Switched Current Source Has Clean,
Predictable Dynamics
delay programming voltage. The fast switching and ramp
linearity permits 1ns accuracy and 100ps repeatability.
Figure 13, a high speed expansion of the current source
turn-on, details the clean switching. Q4 goes off within 2ns
of the trigger input (Trace A) dropping low, enabling the
current source (Q2’s emitter is Trace C). Concurrently, the
1000pF capacitor’s ramp (Trace B) begins. The LT1394’s
output (Trace D) drops low about 7ns later, returning high
after crossing (in this case) a relatively low programming
voltage. Figure 14 juxtaposes the waveforms differently,
permitting enhanced study of circuit timing. Switching
begins with the input trigger falling low (Trace A). The ramp
(Trace C) begins 3ns after the current source turns on (Q2
emitter is Trace D). The output pulse (Trace B) begins
about 4ns later.
To calibrate this circuit apply a trigger input and 3V to the
programming input. Adjust the 100trim for a 300ns
width at the LT1394’s output.
A = 5V/DIV
B = 2V/DIV
C = 5V/DIV
D = 5V/DIV
100ns/ DIV
1394 F12
Figure 12. Voltage-Controlled Delay’s Waveforms.
Programming Voltage Determines Delay Between Input
(Trace A) Falling Edge and Output (Trace D) Rising Edge.
High Linearity Timing Ramp (Trace B) Permits 1ns
Accuracy and 100ps Repeatability
A = 2V/DIV
B = 0.1V/DIV
C = 2V/DIV
D = 2V/DIV
10ns/ DIV
1394 F13
Figure 13. High Speed Expansion of Figure 12. Ramp
(Trace B) Begins When Trigger (Trace A) Falls and
Current Source Turns On (Trace C). Trace D is Output
A = 1V/DIV
B = 1V/DIV
C = 0.1V/DIV
D = 1V/DIV
10ns/ DIV
1394 F14
Figure 14. Delay’s Output Switching Begins with
Trigger Falling Low (Trace A). Ramp (Trace C) Starts
3ns After Current Source Turn-On (Trace D). Output
(Trace B) Begins 4ns Later
12
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