LT1533C View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT1533C' PDF : 20 Pages View PDF
LT1533
APPLICATIONS INFORMATION
Thermal Considerations
Computing power dissipation for this IC requires careful
attention to detail. Reduced output slewing causes the part
to dissipate more power than would occur with fast edges.
However, much improvement in noise can be produced
with modest decrease in supply efficiency.
Power dissipation is a function of topology, input voltage,
switch current and slew rates. It is impractical to come up
with an all-encompassing formula. It is therefore recom-
mended that package temperature be measured in each
application. The part has an internal thermal shutdown to
prevent device destruction, but this should not replace
careful thermal design.
1. Dissipation due to input current:
PVIN
=
VIN11mA
+
I
60
where I is the average switch current.
2. Dissipation due to the drivers saturation:
PVSAT = (VSAT)(I)(DCMAX)
where VSAT is the output saturation voltage which is
approximately 0.1 + (0.4)(I), DCMAX is the maximum
duty cycle.
3. Dissipation due to output slew using approximations
for slew rates:
( ( ) ) ( ) () ( ) ( ) ( ) PSLEW
=
VIN
I2
+
∆I2
4
33 109
RCSL
+
I
2
VIN
−
VSAT2
4
220 109
RVSL
fOSC
Note if VSAT and ∆I are small with respect to VIN and I,
then:
()( ) ( )( ) ( )( )() PSLEW
=
( ) ( )
I RCSL +
33 109
VIN
R VSL
220
109
fOSC
VIN
I
where ∆I is the ripple current in the switch, RCSL and
RVSL are the slew resistors and fOSC is the oscillator
frequency.
Power dissipation PD is the sum of these three terms. Die
junction temperature is then computed as:
TJ = TAMB + (PD)(θJA)
where TAMB is ambient temperature and θJA is the package
thermal resistance. For the 16-pin SO θJA is 100°C/W.
For example, with fOSC = 40kHz, VIN = 10V, 0.4A average
current and 0.1A of ripple, the maximum duty cycle is
44%. Assume slew resistors are both 17k and VSAT is
0.26V, then:
PD = 0.176W + 0.094W + 0.158W = 0.429W
In an S16 package the die junction temperature would be
43°C above ambient.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier (VC
pin). Referring to Figure 3, the main pole is formed by
capacitor CVC and the output impedance of the error
amplifier (approximately 400kΩ). The series resistor RVC
creates a “zero” which improves loop stability and tran-
sient response. A second capacitor CVC2, typically one-
tenth the size of the main compensation capacitor, is
sometimes used to reduce the switching frequency ripple
on the VC pin. VC pin ripple is caused by output voltage
ripple attenuated by the output divider and multiplied by
the error amplifier. Without the second capacitor, VC pin
ripple is:
( )( )( )( ) VC PIN RIPPLE =
1.25
VRIPPLE gm
VOUT
RVC
where VRIPPLE = Output ripple (VP-P)
gm = Error amplifier transconductance
RVC = Series resistor on VC pin
VOUT = DC output voltage
10
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