LT1676 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT1676' PDF : 16 Pages View PDF
LT1676
APPLICATIONS INFORMATION
frequency resonance problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power path. B field (magnetic) radiation is minimized by
keeping output diode, switch pin and intput bypass
capacitor leads as short as possible. E field radiation is
kept low by minimizing the length and area of all traces
connected to the switch pin (VSW). A ground plane should
always be used under the switcher circuitry to prevent
interplane coupling.
The high speed switching current path is shown schemati-
cally in Figure 3. Minimum lead length in these paths is
essential to ensure clean switching and minimal EMI. The
paths containing the input capacitor, output switch and
output diode are the only ones containing nanosecond rise
and fall times. Keep these paths as short as possible.
Additionally, it is possible for the LT1676 to cause EMI
problems by “coupling to itself”. Specifically, this can
occur if the VSW pin is allowed to capacitively couple in an
uncontrolled manner to the part’s high impedance nodes,
+
VIN
C1
VIN
LT1676
VSW
L1
+
VOUT
D1
C2
1676 F03
Figure 3. High Speed Current Switching Paths
i.e., SHDN, SYNC, VC and FB. This can cause erratic
operation such as odd/even cycle behavior, pulse width
“nervousness”, improper output voltage and/or prema-
ture current limit action.
As an example, assume that the capacitance between the
VSW node and a high impedance pin node is 0.1pF, and
further assume that the high impedance node in question
exhibits a capacitance of 1pF to ground. Due to the high
dV/dt, large excursion behavior of the VSW node, this will
couple a nearly 5V transient to the high impedance pin,
causing abnormal operation. (This assumes the “typical”
48VIN to 5VOUT application.) An explicit 100pF capacitor
added to the node will reduce the amplitude of the distur-
bance to more like 50mV (although settling time will
increase).
Specific pin recommendations are as follows:
SHDN: If unused, add a 100pF capacitor to ground.
SYNC: Ground if unused.
VC: Add a capacitor directly to ground in addition to the
explicit compensation network. A value of one-tenth of
the main compensation capacitor is recommended, up
to a maximum of 100pF.
FB: Assuming the VC pin is handled properly, this pin
usually requires no explicit capacitor of its own, but
keep this node physically small to minimize stray ca-
pacitance.
TYPICAL APPLICATIONS
Minimum Component Count Application
Figure 4a shows a basic “minimum component count”
application. The circuit produces 5V at up to 500mA IOUT
with input voltages in the range of 12V to 48V. The typical
POUT/PIN efficiency is shown in Figure 4b. No pulse
skipping is observed down to zero external load. As
shown, the SHDN and SYNC pins are unused, however
either (or both) can be optionally driven by external signals
as desired.
User Programmable Undervoltage Lockout
Figure 5 adds a resistor divider to the basic application.
This is a simple, cost-effective way to add a user-program-
mable undervoltage lockout (UVLO) function. Resistor R5
is chosen to have approximately 200µA through it at the
nominal SHDN pin lockout threshold of roughly 1.25V.
The somewhat arbitrary value of 200µA was chosen to be
significantly above the SHDN pin input current to minimize
its error contribution, but significantly below the typical
3.2mA the LT1676 draws in lockout mode. Resistor R4 is
then chosen to yield this same 200µA, less 2.5µA, with the
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