Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

LT3973 View Datasheet(PDF) - Linear Technology

Part Name
Description
MFG CO.
'LT3973' PDF : 24 Pages View PDF
Prev 21 22 23 24
LT3973/LT3973-3.3/LT3973-5
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD PackDaDgePackage
10-Lead10P-laLsetaicdDPFlaNs(t3icmDmFN× 3(3mmmm) × 3mm)
(Referen(cReeLfTeCreDnWceGL#TC05D-W08G-1#69095R-0e8v-C1)699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
TYP
6
0.40 ±0.10
10
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
3.00 ±0.10 1.65 ±0.10
(4 SIDES) (2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
0.75 ±0.05
(DD) DFN REV C 0310
5
1
0.25 ±0.05
0.50 BSC
0.00 – 0.05
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
For more information www.linear.com/LT3973
3973fb
21
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]