LT4356-3 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT4356-3' PDF : 24 Pages View PDF
LT4356-3
APPLICATIONS INFORMATION
VIN
12V
D2*
SMAJ58CA
RSNS
10mΩ
Q2
Si4435
D1
1N5245
15V
R6
10k
5
SNS
6 VCC
Q1
IRLR2908
R3
10Ω
4
GATE
3
OUT
FB 2
7 SHDN
11 AOUT
12 IN+
*DIODES INC.
LT4356DE-3
GND
10
TMR
1
CTMR
0.1µF
FLT 8
EN 9
43563 F08
VOUT
12V, 3A
CLAMPED AT 16V
R1
59k
R2
4.99k
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
Shutdown
The LT4356-3 can be shut down to a low current mode
when the voltage at the SHDN pin goes below the shutdown
threshold of 0.6V. The quiescent current drops to 7µA. All
functions are turned off including the auxiliary amplifier.
After the GATE pin pulls low due to a fault time out, the
LT4356-3 latches off. Allow sufficient time for the TMR pin
to discharge to 0.5V (typical discharge current is 2.2µA)
and for the MOSFET to cool before attempting to reset the
part. To reset, pull the SHDN pin low for at least 100µs,
then pull high with a slew rate of at least 10V/ms.
The SHDN pin can be pulled up to VCC or below GND by
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
current at the pin should be limited to no more than 1µA
if no pull up device is used to help turn it on.
Supply Transient Protection
The LT4356-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. Nevertheless,
voltage transients above 100V may cause permanent dam-
age. During a short-circuit condition, the large change in
current flowing through power supply traces and associated
VIN
D2
SMAJ58A
RSNS
Q1
10mΩ IRLR2908
R4
383k
R5
100k
UNDERVOLTAGE
6 VCC
7 SHDN
12 IN+
11 AOUT
R3
10Ω
54
3
SNS GATE OUT
FB 2
LT4356DE-3
GND
10
EN 9
TMR
FLT 8
1
43563 F09
CTMR
47nF
CL*
22µF
R1
59k
R2
4.99k
VCC
DC-DC
CONVERTER
SHDN GND
FAULT
*SANYO 25CE22GA
Figure 9. Overvoltage Regulator with Low-Battery Detection
wiring can cause inductive voltage transients which could
exceed 100V. To minimize the voltage transients, the power
trace parasitic inductance should be minimized by using
wide traces. A small surge suppressor, D2, in Figure 9,
at the input will clamp the voltage spikes.
A total bulk capacitance of at least 22µF low ESR is required
close to the source pin of MOSFET Q1. In addition, the
bulk capacitance should be at least 10 times larger than
the total ceramic bypassing capacitor on the input of the
DC/DC converter.
Layout Considerations
To achieve accurate current sensing, Kelvin connection
to the current sense resistor (RSNS in Figure 9) is recom-
mended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530µΩ/square. Small resistances can cause large errors in
high current applications. Noise immunity will be improved
significantly by locating resistive dividers close to the pins
with short VCC and GND traces.
Design Example
As a design example, take an application with the following
specifications: VCC = 8V to 14V DC with transient up to 80V,
VOUT ≤ 16V, current limit (ILIM) at 5A, low battery detection
at 6V, and 1ms of overvoltage early warning (Figure 9).
43563fb
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