LT5537 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT5537' PDF : 16 Pages View PDF
LT5537
APPLICATIO S I FOR ATIO
Table 3. Application Design Examples
DESIGN
NUMBER C1, C2
1
15nF
2
100pF
3
5pF
4
47nF
Bold = dominant pole
C6
Open
33nF
390pF
2.2µF
INPUT
POLE
8.5kHz
1.3MHz
20MHz
2.8kHz
INTERNAL
POLE
414kHz
740Hz
50kHz
10Hz
DC
REJECTION BW
1.13MHz
160kHz
10MHz
2kHz
DC
LOOP PM
75°
84°
60°
57°
LOWEST
OPERATING
FREQUENCY
1.13MHz
1.3MHz
20MHz
2.8kHz
APPLICATIONS
Minimal Component Count
General Purpose
HF, Fast Settling
Very Low Frequency
Low Frequency Operation
Because the limiting amplifier stages of the LT5537 are DC
coupled, the high overall gain requires DC offset control.
The LT5537 has internal DC offset cancellation circuitry. The
voltage at the output of the limiting amplifier is low-pass
filtered, inverted and fed back to the input of the limiting
amplifier. The DC cancellation also reduces the gain of the
amplifier at low frequency. As a result, the LT5537 has a
bandpass frequency response with a lower end determined
by the bandwidth of the offset cancellation feedback loop.
The equivalent circuit of the loop filter is shown in Fig-
ure 10. C1 and C2 are the external DC blocking capacitors
of the differential inputs; C6 is an optional external filter
capacitor which is in parallel with an on-chip filter capaci-
tor (CINT = 60pF). For analysis purposes only, the values
for C6 and the on-chip filter capacitor are doubled when a
single-ended equivalent circuit is derived from a differen-
tial implementation.
C1 OR C2
5.5k
7k
2 • C6
2 • CINT 1.5k
RS/2
5537 F16
Figure 10. Offset Cancellation Loop Filter
The optional capacitance (C6) placed between CAP+ (Pin
4) and CAP– (Pin 5) together with the input DC blocking
capacitors C1 and C2 are used to adjust the operating
frequency range. The DC offset cancellation loop contains
two poles and one zero (in the low frequency region for the
purpose of this analysis). The loop filter capacitance (C6
+ CINT) generates one of the two poles, the input AC
coupling capacitors (C1 and C2) determine the other pole
and the input termination resistance leads to the zero.
(The pole associated with the input AC coupling capacitor
also sets the lower corner frequency of the signal path).
The presence of the two poles in the circuit enables two
approaches to the design of the application circuit for a
desired frequency response. But stability margin has to
be ensured in order to avoid ringing in response to any
input transient. Table 3 lists four low frequency loop
designs suitable for different applications.
Design 1 is the simplest application circuit. The external
capacitor C6 is not used. The input pole is set by the AC
coupling capacitors (C1, C2) and is the dominant pole at
8.5kHz. The zero generated by the input coupling capacitor
and the termination resistor is at 60 times the input pole
frequency. The second pole set by the on-chip filter
capacitor (CINT) should be at approximately the same
frequency as that of the zero. This design has a stability
phase margin (PM) of 75 degrees.
5537fa
12
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