LT5571
APPLICATIONS INFORMATION
VCC
EN
75k 25k
overheating. R1 (optional) limits the EN pin current in the
event that the EN pin is pulled high while the VCC inputs
are low. The application board PCB layouts are shown in
Figures 8 and 9.
5571 F06
Figure 6. EN Pin Interface
full chip supply current could be sourced through the EN
pin ESD protection diodes, which are not designed for this
purpose. Damage to the chip may result.
Evaluation Board
Figure 7 shows the evaluation board schematic. A good
ground connection is required for the LT5571’s Exposed
Pad. If this is not done properly, the RF performance will
degrade. Additionally, the Exposed Pad provides heat sink-
ing for the part and minimizes the possibility of the chip
J1
BBIM
R2
49.9Ω
J2
BBIP
R5
49.9Ω
VCC
16 15
14 13
VCC EN
R1
100Ω 1 BBMI GND
EN
BBPI VCC
12
GND
J4
LO IN
2
GND
3
LO
LT5571
11
RF
10
GND
4
GND
9
GND
17
GND
BBMQ GND BBPQ VCC
5 678
C1
100nF
J3
RF
OUT
J5
BBQM
R3
49.9Ω
BOARD NUMBER: DC944A
C2
100nF
R4
49.9Ω
J6
BBQP
5571 F07
Figure 7. Evaluation Circuit Schematic
Figure 8. Component Side of Evaluation Board
Figure 9. Bottom Side of Evaluation Board
5571f
12