LTC1090CJ View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1090CJ' PDF : 28 Pages View PDF
LTC1090
APPLICATIO S I FOR ATIO
serial formats (see Table 2). If an MPU without a serial
interface is used, then 4 of the MPU’s parallel port lines can
be programmed to form the serial link to the LTC1090.
Included here are three serial interface examples and one
example showing a parallel port programmed to form the
serial interface.
Table 2. Microprocessors with Hardware Serial Interfaces
Compatible with the LTC1090**
PART NUMBER
TYPE OF INTERFACE
Motorola
MC6805S2, S3
SPI
MC68HC11
SPI
MC68HC05
SPI
RCA
CDP68HC05
Hitachi
HD6305
HD63705
HD6301
HD63701
HD6303
National Semiconductor
COP400 Family
COP800 Family
NS8050U
HPC16000 Family
SPI
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
MICROWIRE†
MICROWIRE/PLUS†
MICROWIRE/PLUS
MICROWIRE/PLUS
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020*
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
*Requires external hardware
**Contact LTC Marketing for interface information for processors not on
this list
†MICROWIRE and MlCROWIRE/PLUS are trademarks of National
Semiconductor Corp.
Serial Port Microprocessors
Most synchronous serial formats contain a shift clock
(SCLK) and two data lines, one for transmitting and one for
receiving. In most cases data bits are transmitted on the
falling edge of the clock (SCLK) and captured on the rising
edge. However, serial port formats vary among MPU
manufacturers as to the smallest number of bits that can
be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers).
They also vary as to the order in which the bits are
transmitted (LSB or MSB first). The following examples
show how the LTC1090 accommodates these differences.
National MICROWIRE (COP420)
The COP420 transfers data MSB first and in 4-bit incre-
ments (nibbles). This is easily accommodated by setting
the LTC1090 to MSB first format and 12-bit word length.
The data output word is then received by the COP420 in
three 4-bit blocks with the final two unused bits filled with
zeroes by the LTC1090.
Hardware and Software Interface to National Semiconductor
COP420 Processor
LTC1090
CS
COP420
GO
ANALOG
SCLK
SK
INPUTS
DIN
SO
DOUT
SI
DOUT from LTC1090 stored in COP420 RAM
Location A
MSB*
B9 B8 B7 B6
first 4 bits
Location A + 1
Location A + 2
B5 B4 B3 B2
LSB
B1 B0 B0 B0
second 4 bits
third 4 bits
*B9 is MSB in unipolar or sign bit in bipolar
LTC1090 • AI11
MNEMONIC
LEI
SC
OGI
LDD
XAS
LDD
NOP
XAS
XIS
NOP
XAS
XIS
RC
NOP
XAS
XIS
OGI
LEI
DESCRIPTION
Enable SlO
Set Carry flag
G0 is set to (CS goes low)
Load first 4 bits of DIN to ACC
Swap ACC with SIO reg. Starts SK Clk
Load 2nd 4 bits of DIN to ACC
Timing
Swap first 4 bits from A/D with ACC. SK continues.
Put first 4 bits in RAM (location A)
Timing
Swap 2nd 4 bits from A/D with ACC. SK continues.
Put 2nd 4 bits in RAM (location A + 1)
Clear Carry
Timing
Swap 3rd 4 bits from A/D with ACC. SK off
Put 3rd 4 bits in RAM (location A + 2)
G0 is set to 1 (CS goes high)
Disable SlO
1090fc
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