LTC1096 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1096' PDF : 28 Pages View PDF
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
CS
CLK
DOUT
tsuCS
tWAKEUP
HI-Z
tCYC
POWER
DOWN
NULL
BIT
Hi-Z
B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
tCONV
tCYC
CS
CLK
DOUT
tsuCS
tWAKEUP
Hi-Z
POWER
DOWN
NULL
BIT
B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7*
(MSB)
tCONV
Hi-Z
10968 F01
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 1. LTC1096(L) Operating Sequence
The wake-up time is inherently provided for the LTC1098(L)
with setup time = 1μs (see Figure 2).
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving sys-
tems. The LTC1098(L) first receives input data and then
transmits back the A/D conversion result (half duplex).
Because of the half duplex operation, DIN and DOUT may
be tied together allowing transmission over just three
wires: CS, CLK and DATA (DIN/DOUT).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1098(L) and starts the
conversion. After one null bit, the result of the conversion
CS
SHIFT MUX
ADDRESS IN
DIN 1
DOUT 1
DIN 2
1 NULL BIT SHIFT A/D CONVERSION
RESULT OUT
DOUT 2
10968 AI01
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
The LTC1096(L) does not require a configuration input
word and has no DIN pin. A falling CS initiates data trans-
feras shown in the LTC1096(L) operating sequence. After
CS falls, the first CLK pulse enables DOUT. After one null
bit, the A/D conversion result is output on the DOUT line.
Bringing CS high resets the LTC1096(L) for the next data
exchange.
10968fc
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