LTC1196-2 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1196-2' PDF : 28 Pages View PDF
LTC1196/LTC1198
APPLICATIONS INFORMATION
3V VERSUS 5V PERFORMANCE COMPARISON
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of five when the supply is reduced to 3V. The converter
slows down somewhat but still gives excellent performance
on a 3V rail. With a 3V supply, the LTC1196 converts in
1.6μs, samples at 450kHz, and provides a 500kHz linear-
input bandwidth.
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise floor is extremely
low, corresponding to a transition noise of less than 0.1LSB.
DC accuracy includes ±0.5LSB total unadjusted error at
5V. At 3V, linearity error is ±0.5LSB while total unadjusted
error increases to ±1LSB.
Table 1. 5V/3V Performance Comparison
LTC1196-1
5V
PDISS
Max fSMPL
Min tCONV
INL (Max)
50mW
1MHz
600ns
0.5LSB
Typical ENOBs
7.9 at 300kHz
Linear Input Bandwidth (ENOBs > 7)
1MHz
LTC1198-1
PDISS
PDISS (Shutdown)
Max fSMPL
Min tCONV
INL (Max)
50mW
15μW
750kHz
600ns
0.5LSB
Typical ENOBs
7.9 at 300kHz
Linear Input Bandwidth (ENOBs > 7)
1MHz
3V
10mW
383kHz
1.6μs
0.5LSB
7.9 at 100kHz
500kHz
10mW
9μW
287kHz
1.6μs
0.5LSB
7.9 at 100kHz
500kHz
TYPICAL APPLICATIONS
PLD Interface Using the Altera EPM5064
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 12-bit counter and an equivalent
74HC595 8-bit shift register as shown in Figure 12. The
circuit works as follows: bringing ENA high makes the CS
output high and the EN input low to reset the LTC1196 and
disable the shift register. Bringing ENA low, the CS output
DATA
CLK
ENA
CLK
12-BIT
CONVERTER
ENA
CS
8-BIT
SHIFT REGISTER
DATA
CLK B0-B7
EN
B0-B7
CS
1196/98 F12
Figure 12. An Equivalent Circuit of the EPM5064
goes high for one CLK cycle with every 12 CLK cycles.
The inverted signal, EN, of the CS output makes the 8-bit
data available on the B0-B7 lines. Figures 13 and 14 show
the interconnection between the LTC1196 and EPM5064
and the timing diagram of the signals between these two
devices. The CLK frequency in this circuit can run up to
fCLK(MAX) of the LTC1196.
VCC CLK
1μF
3, 14, 25, 36
1 CS
8
VCC
+
2
+IN
7
CLK
–
3
–IN
LTC1196
6
DOUT
4
GND
5
VREF
RESERVE PINS OF EPM5064:
2, 4-8,15-20, 22, 24, 26-30
33 ENA
B7 1
23
37
EPM5064 38
34
CLK
39
35
40
DATA
41
42
44
B0
9-13, 21,
31, 32, 43
1196/98 F13
Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD
119698fa
23
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