APPLICATI S I FOR ATIO
2.42V*
VREF
OUTPUT
ANALOG INPUT
(0V TO 5V) 10Ω*
10µF
0.1µF
µP
DATA
BUS
LTC1272
A IN
VREF
AGND
VDD
NC✝
BUSY
D11 (MSB) CS
D10
RD
D9
HBEN
D8 CLK OUT
D7
CLK IN
D6
D0/8
D5
D1/9
D4
D2/10
DGND D3/11
LTC1272
0.1µF
–15V
10µ F
†
0.1µF
5V
10µ F
S
Q 1/2 D**
74HC74
CLK
74HC04
RD
µP
CONTROL
LINES
EXTERNAL
ASYNCHRONOUS OR
CLOCK
* THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V
REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER
OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE
10Ω RESISTOR.
** THE D FLIP-FLOP SYNCHRONIZES THE CONVERSION START SIGNAL (RD ) TO THE
ADC CLKOUT SIGNAL TO PREVENT OUTPUT CODE NOISE WHICH OCCURS WITH
AN ASYNCHRONOUS CLOCK.
✝ THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES
NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.
Figure 23. Plugging the LTC1272 into an AD7572 Socket
Case 2: Clock Not Synchronous with CS and RD
LTC1272 • TA05
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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