LTC1274 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1274' PDF : 20 Pages View PDF
LTC1274/LTC1277
APPLICATI S I FOR ATIO
adjusted before full-scale error. Bipolar offset error ad-
justment is achieved by trimming the offset adjust while
the input voltage is 0.5LSB below ground. This is done by
applying an input voltage of – 0.50mV (– 0.5LSB) to the
input in Figure 11c and adjusting the R8 until the ADC’s
output code flickers between 0000 0000 0000 and 1111
1111 1111 in LTC1274 or between 0111 1111 1111 and
1000 0000 0000 in LTC1277. For full-scale adjustment, an
input voltage of 2.0465V (FS – 1.5LSBs) is applied to the
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111 in LTC1274
or between 1111 1111 1110 and 1111 1111 1111 in
LTC1277.
Internal Clock
The A/D converters have an internal clock that eliminates
the need of synchronization between the external clock
and the CS and RD signals found in other ADCs. The
internal clock is factory trimmed to achieve a typical
conversion time of 6µs. No external adjustments are
required and with the maximum acquisition time of 2µs
throughput performance of 100ksps is assured.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs in the LTC1274: CS, CONVST and
RD. For the LTC1277 there are four digital inputs: CS,
CONVST, RD and HBEN. Figure 12 shows the logic
structure associated with these inputs for LTC1277. A
falling edge on CONVST will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output and this
is low while conversion is in progress. The High Byte
Enable input (HBEN) in the LTC1277 is to multiplex the 12
bits of conversion data onto the lower D7 to D0/8
outputs.
Figures 13 through 17 show several different modes of
operation. In modes 1a and 1b (Figures 13 and 17) CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
R1
50Ω
V1
+
A1
–
R4
R2
100Ω
10k
R3
10k
FULL-SCALE
ADJUST
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
AIN (LTC1274)
AIN+ (LTC1277)
LTC1274
LTC1277
AGND
AIN– (LTC1277)
LTC1274/77 F11a
Figure 11a. Full-Scale Adjust Circuit
ANALOG R1
INPUT 10k
0V TO
+
4.096V
R2
10k
–
10k
5V
R9
20Ω
R3
100k
R6
400Ω
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
5V
R7
R8
100k
10k
OFFSET
ADJUST
AIN (LTC1274)
AIN+ (LTC1277)
LTC1274
LTC1277
AIN– (LTC1277)
LTC1274/77 F11b
Figure 11b. LTC1274/LTC1277 Unipolar Offset and
Full-Scale Adjust Circuit
R1
ANALOG 10k
INPUT
+
R2
10k
–
R3
100k
R6
200Ω
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
5V
R7
R8
100k
20k
OFFSET
ADJUST
– 5V
AIN (LTC1274)
AIN+ (LTC1277)
LTC1274
LTC1277
AIN– (LTC1277)
LTC1274/77 F11c
Figure 11c. LTC1274/LTC1277 Bipolar Offset and
Full-Scale Adjust Circuit
16
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