LTC1279ISW View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1279ISW' PDF : 16 Pages View PDF
LTC1279
APPLICATI S I FOR ATIO
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CS, CONVST and RD. Figure 11
shows the logic structure associated with these inputs. A
logic “0” for CONVST will start a conversion after the ADC
has been selected (i.e., CS is low). Once initiated, it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output, and this is low
while conversion is in progress.
Figures 12 through 16 show several different modes of
operation. In modes 1a and 1b (Figures 12 and 13) CS and
RD are both tied low. The falling CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 14) CS is tied low. The falling CONVST
signal again starts the conversion. Data outputs are in
three-state until read by MPU with the RD signal. Mode 2
can be used for operation with a shared MPU databus.
In Slow memory and ROM modes (Figures 15 and 16) CS
is tied low and CONVST and RD are tied together. The MPU
starts conversion and reads the output with the RD signal.
Conversions are started by the MPU or DSP (no external
sample clock).
In Slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode, the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the previ-
ous conversion result. After the conversion is complete,
the processor can read the new result (which will initiate
another conversion).
RD
CS
CONVST
SHDN
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
BUSY
D
Q
CONVERSION
START (RISING
EDGE TRIGGER)
FLIP
FLOP
CLEAR
1279 F11
Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN
CS = RD = 0
CONVST
tCONV
t4
SAMPLE N
SAMPLE N + 1
t5
BUSY
DATA
DATA (N – 1)
DB11 TO DB0
t6
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
1279 F12
Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled. (CONVST =
)
14
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