LTC1282 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1282' PDF : 24 Pages View PDF
APPLICATI S I FOR ATIO
LTC1282
HBEN
CS
RD
BUSY
DATA
HOLD
TRACK
t8
t9
t1
t5
t4
t2
tCONV
t3
t7
OLD DATA
DB7-DB0
t12
t8
t9
t8
t9
t1
t5
t4
t10
t11
t3
t7
NEW DATA
DB11-DB8
t1
t4
t5
t2
t3
t7
NEW DATA
DB7-DB0
t12
LTC1282 • F19
Figure 19. ROM Mode Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read (New Data)
Low
Low
Low
Low
DB11
DB10
DB9
DB8
Third Read (New Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
A16
A1
ADDRESS BUS
IS
TMS320C25
READY
R/W
D16
D0
EN
ADDRESS
DECODE
DATA BUS
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1282
CS
BUSY
RD
D11
D0/8 HBEN
LTC1282 • F20
Figure 20. TMS320C25 Interface
where D is Data Memory Address and PA is the PORT
ADDRESS.
MC68000 Microprocessor
Figure 21 shows a typical interface for the MC68000. The
LTC1282 is operating in the Slow Memory Mode. Assum-
ing the LTC1282 is located at address C000, then the
following single 16-bit MOVE instruction both starts a
conversion and reads the conversion result:
Move.W $C000,D0
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
19
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