LTC1283 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1283' PDF : 24 Pages View PDF
LTC1283
APPLICATI S I FOR ATIO
Hardware and Software Interface to National Semiconductor
COP820C Processor
ANALOG
INPUTS
LTC1283
CS
SCLK
•
•
•
DIN
•
DOUT
COP820C
G1
SK
SO
SI
LTC1283 • AI11
MNEMONIC
LD (F0)←0D
LD (D5)←32
LD (EE)←8
LD (B)←D4
LD (A)←(F0)
RBIT 1
X (A)←→(E9)
LD (B)←EF
SBIT 2
↑
NOP
↓
COMMENTS
LOAD 0D INTO F0 (DIN)
CONFIGURE PORT G
CONFIGURE CONTROL REG.
PORT G DATA REG. INTO B
LOAD DIN INTO ACC
G1 RESET (CS GOES LOW)
LOAD DIN INTO SHIFT REG.
LOAD PSW REG. ADDR IN B
TRANSFER BEGINS
15 NOPs FOR TIMING
Motorola SPI (MC68HC05C4, MC68HC11)
The MC68HC05C4 and MC68HC11 transfer data MSB-
first and in 8-bit increments. Programming the LTC1283
for MSB-first format and 16-bit word length allows the 10-
Hardware and Software Interface to Motorola MC68HC05C4 and
MC68HC11 Processors
ANALOG
INPUTS
LTC1283
CS
SCLK
•
•
•
DIN
•
DOUT
MC68HC05C4
MC68HC11
C0
SCK
MOSI
MISO
LTC1283 • AI13
MNEMONIC
BCLR n
LDA
STA
↑
NOP
↓
LDA
LDA
STA
COMMENTS
C0 IS CLEARED (CS GOES LOW)
LOAD DIN FOR LTC1283 INTO ACC
LOAD DIN FROM ACC TO SPI DATA REG. START SCK
8 NOPs FOR TIMING
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LOAD LTC1283 DOUT FROM SPI DATA REG.
INTO ACC (BYTE 1)
LOAD LTC1283 DOUT INTO RAM (LOCATION A)
DOUT from LTC1283 stored in COP820C RAM
MSB*
9 8 7 6 5 4 3 2 BYTE 1
LSB
1 0 X X X X X X BYTE 2
*B9 is MSB in unipolar or sign bit in bipolar
LTC1283 • AI12
MNEMONIC
X(A)←→(E9)
SBIT 2
X (A)←→(F3)
RBIT 2
LD (B)←D4
SBIT 1
X (A)←→(E9)
RC
RRCA
RRCA
RRCA
X (A)←→(F4)
COMMENTS
LOAD DOUT INTO ACC
TRANSFER CONTINUES
LOAD DOUT IN ADDR F3
STOP TRANSFER
PUT PORT G ADDR IN B
G1 SET (CS GOES HIGH)
LOAD DOUT INTO ACC
CLEAR CARRY
SHIFT RIGHT THRU CARRY
SHIFT RIGHT THRU CARRY
SHIFT RIGHT THRU CARRY
LOAD DOUT IN ADDR F4
bit data output to be received by the MPU as two 8-bit
bytes with the final 6 unused bits filled with zeroes by the
LTC1283.
DOUT from LTC1283 stored in MC68HC05C4 or MC68HC11 RAM
MSB*
LOCATION A B9 B8 B7 B6 B5 B4 B3 B2 BYTE 1
LSB
LOCATION A + 1 B1 B0 0 0 0 0 0 0 BYTE 2
*B9 is MSB in unipolar or sign bit in bipolar
LTC1283 • AI14
MNEMONIC
STA
↑
NOP
↓
BSET n
LDA
LDA
STA
COMMENTS
START NEXT SPI CYCLE
6 NOPs FOR TIMING
CO IS SET (CS GOES HIGH)
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LOAD LTC1283 DOUT FROM SPI DATA REG.
INT ACC (BYTE 2)
LOAD LTC1283 INTO RAM (LOCATION A +1)
14
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