LTC1291
APPLICATI S I FOR ATIO
SAMPLE
HOLD
CS
CLK
DIN
DOUT
(+) INPUT
(–) INPUT
SGL/
START
DIFF
HI-Z
ODD/
SIGN
MSBF
PS
tSMPL
“+” INPUT MUST SETTLE DURING THIS TIME
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
Figure 9. “+” and “–” Input Settling Windows
B11
LTC1291 F09
HORIZONTAL: 500ns/DIV
Figure 10. Adequate Settling of Op Amp Driving Analog Input
HORIZONTAL: 20µs/DIV
Figure 11. Poor Op Amp Settling Can Cause A/D Errors
(Note Horizontal Scale)
1291fa
16