LTC1292 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1292' PDF : 24 Pages View PDF
APPLICATI
CS
S I FOR ATIO
tWHCS
LTC1292/LTC1297
CLK
DOUT
(+) INPUT
(–) INPUT
CS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
HI-Z
B11
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
B10
B9
Figure 11b. Setup Time (tsuCS) Is Met for the LTC1292
tWHCS
LTC1292/7 F11b
CLK
DOUT
(+) INPUT
(–) INPUT
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
HI-Z
B11
B10
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
Figure 11c. Setup Time (tsuCS) Is Not Met for the LTC1292
LTC1292/7 F11c
tsuCS. With the minimum possible sample time of 6µs,
RSOURCE+ < 5k and C1 < 20pF will provide adequate
settling time. In general for both the LTC1292 and LTC1297
keep the product of the total resistance and the total
capacitance less than tSMPL/ 9. If this condition can not be
met, then make C1 > 0.47µF (see RC Input Filtering
section).
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 11a,
11b, 11c and 12). During the conversion, the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. It is critical that the
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