LTC1343 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1343' PDF : 28 Pages View PDF
LTC1343
APPLICATIONS INFORMATION
Echoed Clock Mode
The LTC1343 contains the logic to generate the echoed
clock when using a serial controller with only two clock
pins. Figure 23 shows the chip in both the DTE and DCE
echoed clock in EIA-530 mode. The control signals are not
shown. The echoed clock configuration is selected by
pulling the EC pin low. On the DTE side the transmit clock
TXC receiver output is connected to the echoed clock,
SCTE, driver input. The TXC pin on the serial controller is
configured as an input. On the DCE side, the transmit clock
from the serial controller is used to generate both TXC and
RXC. A phase inverter is placed in the TXC signal path on
both the DTE and DCE side to help correct phase problems
with long cables. If the Invert pin is high, the phase of the
data is inverted.
Loop-Back
The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 24 shows
a complete DTE interface in the loop-back configuration
with the EC pin pulled high. The loop-back configuration is
selected by pulling the LB pin low. Both the line side and
logic side signals are looped back. The DCE loop-back
configuration is shown in Figure 25.
If the echoed clock mode is selected by pulling EC low, D3
becomes an output and is connected to receiver 2’s output
R3 in DTE mode as shown in Figure 26. In the echoed clock
DCE loop-back mode, driver 4 is connected to driver 3’s
input D3 as shown in Figure 27.
SERIAL
CONTROLLER
LL
TXD
DTE
LTC1343
D1
D2
TXC
D3
INVERT
D4
R1
RXC
R2
RXD
R3
TM
R4
LTC1344
LL
TXD
SCTE
LTC1344
103Ω
103Ω
103Ω
TXC
103Ω
RXC
103Ω
RXD
TM
DCE
LTC1343
R4
R3
R2
SERIAL
CONTROLLER
LL
RXD
RXC
R1
D4
INVERT
D3
TXC
D2
TXD
D1
TM
1 01 00 10 0
1 010 0
1 0110
1 01 01 10 0
1343 F23
Figure 23. EIA-530 Echoed Clock Configuration
14
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