LTC1392CS8 View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC1392CS8

Micropower Temperature, Power Supply and Differential Voltage Monitor

Linear Technology 

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LTC1392

TEST CIRCUITS

Load Circuit for tdDO, tr and tf

1.4V

DOUT

3k

100pF

TEST POINT

LTC1392 • TC02

Voltage Waveforms for DOUT Rise and Fall Times, tr and tf

DOUT

VOH

VOL

tr

tf

1392 TC04

Load Circuit for tdis and ten

TEST POINT

DOUT

3k

100pF

5V tdis WAVEFORM 2, ten

tdis WAVEFORM 1

LTC1392 • TC05

Voltage Waveforms for DOUT Delay Time, tdDO

CLK

DOUT

VIL

tdDO

VOH

LTC1392 • TC03

VOL

Voltage Waveforms for tdis

CS

2.0V

DOUT

WAVEFORM 1

(SEE NOTE 1)

DOUT

WAVEFORM 2

(SEE NOTE 2)

90%

tdis

10%

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNTIL DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNTIL DISABLED BY THE OUTPUT CONTROL.

LTC1392 • TC06

APPLICATIONS INFORMATION

The LTC1392 is a micropower data acquisition system

designed to measure temperature, an on-chip power

supply voltage and a differential input voltage. The LTC1392

contains the following functional blocks:

1. On-chip temperature sensor

2. 10-bit successive approximation capacitive ADC

3. Bandgap reference

4. Analog multiplexer (MUX)

5. Sample-and-hold (S/H)

6. Synchronous, half-duplex serial interface

7. Control and timing logic

DIGITAL CONSIDERATIONS

Serial Interface

The LTC1392 communicates with microprocessors and

other external circuitry via a synchronous, half-duplex,

3-wire serial interface (see Figure 1). The clock (CLK)

synchronizes the data transfer with each bit being trans-

mitted on the falling CLK edge and captured on the rising

CLK edge in both transmitting and receiving systems. The

input data is first received and then the A/D conversion

result is transmitted (half-duplex). Half-duplex operation

allows DIN and DOUT to be tied together allowing transmis-

sion over three wires: CS, CLK and DATA (DIN/DOUT). Data

transfer is initiated by a falling chip select (CS) signal. After

the falling CS is recognized, an 80µs delay is needed for

6

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