LTC1418 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1418' PDF : 30 Pages View PDF
LTC1418
APPLICATIONS INFORMATION
CS = 0
tCONV
t8
(SAMPLE N)
RD = CONVST
t6
t11
BUSY
DATA
t10
DATA (N – 1)
DB13 TO DB0
t7
DATA N
DB13 TO DB0
DATA N
DB13 TO DB0
Figure 18. Slow Memory Mode Timing
DATA (N + 1)
DB13 TO DB0
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CS = 0
RD = CONVST
BUSY
DATA
tCONV
t8
(SAMPLE N)
t6
t11
t10
DATA (N – 1)
DB13 TO DB0
Figure 19. ROM Mode Timing
DATA N
DB13 TO DB0
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serial function names: EXT/INT, DOUT, CLKOUT, SCLK and
EXTCLKIN.) As in parallel mode, conversions are started by
a falling CONVST edge with CS low. After a conversion is
completed and the output shift register has been updated,
BUSY will go high and valid data will be available on DOUT
(Pin 19). This data can be clocked out either before the
next conversion starts or it can be clocked out during the
next conversion. To enable the serial data output buffer
and shift clock, CS and RD must be low.
Figure 20 shows a function block diagram of the LTC1418
in serial mode. There are two pieces to this circuitry: the
conversion clock selection circuit (EXT/INT, EXTCLKIN and
CLKOUT) and the serial port (SCLK, DOUT, CS and RD).
Conversion Clock Selection (Serial Mode)
In Figure 20, the conversion clock controls the internal
ADC operation. The conversion clock can be either internal
or external. By connecting EXT/INT low, the internal clock
is selected. This clock generates 16 clock cycles which
feed into the SAR for each conversion.
To select an external conversion clock, tie EXT/INT high
and apply an external conversion clock to EXTCLKIN
(Pin 16). (When an external shift clock (SCLK) is used
during a conversion, the SCLK should be used as the
external conversion clock to avoid the noise generated
by the asynchronous clocks. To maintain accuracy the
external conversion clock frequency must be between
30kHz and 4.5MHz.) The SAR sends an end of conversion
signal, EOC, that gates the external conversion clock so
that only 16 clock cycles can go into the SAR, even if the
external clock, EXTCLKIN, contains more than 16 cycles.
When CS and RD are low, these 16 cycles of conversion
clock (whether internally or externally generated) will ap-
pear on CLKOUT during each conversion and then CLK-
OUT will remain low until the next conversion. If desired,
CLKOUT can be used as a master clock to drive the serial
port. Because CLKOUT is running during the conversion,
it is important to avoid excessive loading that can cause
large supply transients and create noise. For the best
performance, limit CLKOUT loading to 20pF.
Serial Port
The serial port in Figure 20 is made up of a 16-bit shift
register and a three-state output buffer that are controlled
by three inputs: SCLK, RD and CS. The serial port has one
output, DOUT, that provides the serial output data.
For more information www.linear.com/LTC1418
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