LTC1435I View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1435I' PDF : 20 Pages View PDF
LTC1435
APPLICATIONS INFORMATION
Foldback Current Limiting
As described in Power MOSFET and D1 Selection, the
worst-case dissipation for either MOSFET occurs with a
short-circuited output, when the synchronous MOSFET
conducts the current limit value almost continuously. In
most applications this will not cause excessive heating,
even for extended fault intervals. However, when heat
sinking is at a premium or higher RDS(ON) MOSFETs are
being used, foldback current limiting should be added to
reduce the current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding diode
DFB between the output and the ITH pin as shown in the
Functional Diagram. In a hard short (VOUT = 0V) the
current will be reduced to approximately 25% of the
maximum output current. This technique may be used for
all applications with regulated output voltages of 1.8V or
greater.
SFB Pin Operation
When the SFB pin drops below its ground referenced
1.19V threshold, continuous mode operation is forced. In
continuous mode, the large N-channel main and synchro-
nous switches are used regardless of the load on the main
output.
In addition to providing a logic input to force continuous
synchronous operation, the SFB pin provides a means to
regulate a flyback winding output. Continuous synchro-
nous operation allows power to be drawn from the auxil-
iary windings without regard to the primary output load.
The SFB pin provides a way to force continuous synchro-
nous operation as needed by the flyback winding.
The secondary output voltage is set by the turns ratio of the
transformer in conjunction with a pair of external resistors
returned to the SFB pin as shown in Figure 4a. The
secondary regulated voltage, VSEC, in Figure 4a is given by:
VSEC ≈ (N + 1)VOUT > 1.191+ RR65
where N is the turns ratio of the transformer and VOUT is
the main output voltage sensed by VOSENSE.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1435 circuits. LTC1435 VIN current, INTVCC
current, I2R losses, and topside MOSFET transition losses.
1. The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. VIN current results in a small
(< 1%) loss which increases with VIN.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INT VCC which is typically much larger than the
control circuit current. In continuous mode,
IGATECHG = f(QT + QB), where QT and QB are the gate
charges of the topside and bottom side MOSFETs.
By powering EXTVCC from an output-derived source,
the additional VIN current resulting from the driver and
control currents will be scaled by a factor of
Duty Cycle/Efficiency. For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi-
mately 3mA of VIN current. This reduces the midcurrent
loss from 10% or more (if the driver was powered
directly from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the topside main
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