LTC1438/LTC1439
APPLICATIONS INFORMATION
Functional Diagram. In a hard short (VOUT = 0V) the current
will be reduced to approximately 25% of the maximum
output current. This technique may be used for all applica-
tions with regulated output voltages of 1.8V or greater.
Phase-Locked Loop and Frequency Synchronization
The LTC1439 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage-controlled oscillator is ±30% around the center
frequency fO.
1.3fO
fO
0.7fO
0
0.5
1.0
1.5
2.0
2.5
VPLLLPF (V)
1438 F07
Figure 7. Operating Frequency vs VPLLLPF
The value of COSC is calculated from the desired operating
frequency (fO). Assuming the phase-locked loop is locked
(VPLLLPF = 1.19V):
COSC
(pF)
=
⎡
⎢
2.1(104 )
⎤
⎥
⎣⎢Frequency (kHz)⎦⎥
−
11
Stating the frequency as a function of VPLLLPF and COSC:
( ) Frequency kHz =
8.4(108 )
⎡
⎤
⎢
⎥
[ ( ) ] COSC pF + 11
⎢
⎢
⎢17µA
⎣⎢
1
+
⎛
18µA⎝⎜
VPLLLPF
2.4V
⎞
⎠⎟
+ 2000⎥⎥
⎥
⎦⎥
18
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆fC:
∆fH = ∆fC = ±0.3 fO.
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLL LPF pin. A simplified block
diagram is shown in Figure 8.
If the external frequency fPLLIN is greater than the oscilla-
tor frequency f0SC, current is sourced continuously, pull-
ing up the PLL LPF pin. When the external frequency is less
than f0SC, current is sunk continuously, pulling down the
PLL LPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLL LPF pin is adjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
EXTERNAL
FREQUENCY
2.4V
PHASE
DETECTOR
PLLIN*
SGND
50k
DIGITAL
PHASE/
FREQUENCY
DETECTOR
RLP
CLP
COSC
PLL LPF*
COSC
OSC
*LTC1439 ONLY
1438 F08
Figure 8. Phase-Locked Loop Block Diagram
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