LTC1592C View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1592C' PDF : 16 Pages View PDF
LTC1588/LTC1589/LTC1592
PI FU CTIO S
IOUT1 (Pin 5): True DAC Current Output. Tied to the
inverting input of the current-to-voltage op amp.
IOUT2 (Pin 6): Complement of DAC Current Output. Nor-
mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system’s analog
ground plane.
GND (Pin 8): Ground. Tie to the system’s analog ground
plane.
VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V.
Requires a 0.1µF bypass capacitor to ground.
SDO (Pin 10): Serial Data Output. Data at this pin is shifted
out on the rising edge of SCK.
SDI (Pin 11): Serial Data Input.
SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
is shifted into the input shift register on rising edge of SCK.
CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCK is enabled for shifting data into the input shift register.
When CS/LD is pulled high, SCK is disabled and the control
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).
CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.
REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to ±15V.
R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
reference input REF (Pin 15) and the output of the inverting
amplifier tied to RCOM (Pin 1).
FU CTIO TABLE
Table 1
Internal Register Status
COMMAND
C3 C2 C1 C0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SREG
BUF1
BUF2
OPERATION
DATA WORD
DAC
DAC
EACH COMMAND IS EXECUTED
Dn IN INPUT
INPUT
BUFFER
OUTPUT
ON THE RISING EDGE OF CS/LD
SHIFT REGISTER BUFFER (DAC OUTPUT) RANGE
Copy Data Word Dn in SReg to Buf1
Dn
Dn
No Change No Change
Copy the Data in Buf1 to Buf2
X
Dn
Dn
No Change
Copy Data Word Dn in SReg to Buf1 and Buf2
Dn
Dn
Dn
No Change
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Dn
Dn
Dn
5V
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Dn
Dn
Dn
10V
Set Range to ±5V. Copy Dn in SReg to Buf1 and Buf2
Dn
Set Range to ±10V. Copy Dn in SReg to Buf1 and Buf2
Dn
Set Range to ±2.5V. Copy Dn in SReg to Buf1 and Buf2
Dn
Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2
Dn
Dn
Dn
±5V
Dn
Dn
±10V
Dn
Dn
±2.5V
Dn
Dn
–2.5V to 7.5V
Reserved (Do Not Use)
No Operation
X
No Change No Change No Change
Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.
1588992fa
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