LTC1608AIG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1608AIG' PDF : 20 Pages View PDF
LTC1608
APPLICATIO S I FOR ATIO
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
±2.5V
ANALOG INPUT
0V TO
5V
1 AIN+
2 AIN–
3 VREF
LTC1608
22µF
4 REFCOMP
5 AGND
1608 F14b
Figure 14b. Selectable 0V to 5V or ±2.5V Input Range
Full-Scale and Offset Adjustment
Figure 15a shows the ideal input/output characteristics
for the LTC1608. The code transitions occur midway
between successive integer LSB values (i.e., – FS +
0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB,
FS – 0.5LSB). The output is two’s complement binary with
1LSB = FS – (– FS)/65536 = 5V/65536 = 76.3µV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error, apply
– 38µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the
AIN– input by varying the output voltage of pin VOUTA from
the LTC1662 until the output code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111. For full-scale
adjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs)
is applied to AIN+ and the output voltage of pin VOUTB is
adjusted until the output code flickers between 0111 1111
1111 1110 and 0111 1111 1111 1111.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best per-
formance from the LTC1608, a printed circuit board with
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
– (FS – 1LSB)
FS – 1LSB
INPUT VOLTAGE (AIN+ – AIN–)
1608 F15a
Figure 15a. LTC1608 Transfer Characteristics
ANALOG
INPUT
1 AIN+
LTC1662
CS/LD VOUTA
SCK GND
SDI
VCC
5V
REF VOUTB
0.1µF
R1
40.2k
R3
1.5M
R2
100Ω
2 AIN–
LTC1608
3 VREF
+
80.6k
1%
2.2µF 4
+
22µF
5
REFCOMP
AGND
OFFSET ADJ RANGE: ±0.125%
–5V
FULL-SCALE ADJ RANGE: ±0.25%
1608 F15b
Figure 15b. Offset and Full-Scale Adjust Circuit
ground plane is required. Layout should ensure that digital
and analog signal lines are separated as much as possible.
Particular care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.The
analog input should be screened by AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other
analog grounds should be connected to this single analog
ground point. The REFCOMP bypass capacitor and the
DVDD bypass capacitor should also be connected to this
analog ground plane. No other digital grounds should be
connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
14
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