LTC1609IG View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1609IG' PDF : 24 Pages View PDF
LTC1609
APPLICATIO S I FOR ATIO
EXTERNAL
DATACLK
t12
0t13
1
t14
2
3
4
16
17
18
t19
CS
R/C
BUSY
SYNC
DATA
TAG
t16
t15
t2
t3
t17
t12
t23
TAG0
t18
B15
(MSB)
t24
TAG1
B14
TAG2
B13
TAG3
B1
B0
TAG0 TAG1
TAG15
TAG16
TAG17
TAG18
TAG19
1606 F12
Figure 12. Conversion and Read Timing Using an External Data Clock (EXT/INT Tied High).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2µs
DCLK IN
R/C IN
CS IN
LTC1609
#2
TAG DATA
CS
R/C
DCLK
LTC1609
#1
TAG DATA
CS
R/C
DCLK
DATA OUT
1609 F13
Figure 13. Two LTC1609s Cascaded
Together Using the TAG Input
bit will be shifted out on the following clock pulse before
the MSB from device #2 becomes available (Figure 14).
The reason for this is the MSB from device #2 will not be
valid soon enough to meet the minimum setup time of
device #1’s TAG input. A minimum of 34 clock pulses are
needed to shift out the results from both LTC1609s
assuming the data is captured on the falling clock edge.
Using the highest frequency permitted for DATACLK
(20MHz), a 200kHz throughput can still be achieved.
1609fa
18
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