LTC1664_1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1664_1' PDF : 16 Pages View PDF
LTC1664
U
OPERATIO
Transfer Function
The transfer function is
VOUT(IDEAL) = 10k24 VREF
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1664 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition. If it is not
possible to sequence the supplies, connect a Schottky
diode from REF (anode) to VCC (cathode).
Serial Interface
Referring to Figure 2: With CS/LD held low, data on the DIN
input is shifted into the 16-bit shift register on the positive
edge of SCK. The 4-bit DAC address, A3-A0, is loaded first
(see Table 2), then the 10-bit input code, D9-D0, ordered
MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are
loaded last. When the full 16-bit input word has been
shifted in, CS/LD is pulled high, loading the DAC register
with the word and causing the addressed DAC output(s)
to update. The clock is disabled internally when CS/LD is
high. Note: SCK must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appears on DOUT 16 positive SCK edges after being applied
to DIN.
Multiple LTC1664’s can be controlled from a single 3-wire
serial port (i.e., SCK, DIN and CS/LD) by using the included
“daisy-chain” facility. A series of m chips is configured by
connecting each DOUT (except the last) to DIN of the next
chip, forming a single 16m-bit shift register. The SCK and
CS/LD signals are common to all chips in the chain. In use,
CS/LD is held low while m 16-bit words are clocked to DIN
of the first chip; CS/LD is then pulled high, updating all of
them simultaneously.
Sleep Mode
DAC address 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The refer-
ence input and analog outputs are set in a high impedance
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Sleep mode is initiated by performing a load sequence to
address 1110b (the DAC input word D9-D0 is ignored).
Once in Sleep mode, a load sequence to any other address
(including “No Change” address 0000b) causes the
LTC1664 to Wake. It is possible to keep one or more chips
of a daisy chain in continuous Sleep mode by giving the
Sleep instruction to these chips each time the active chips
in the chain are updated.
Table 1. LTC1664 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Address/Control
Input Code
Don’t
Care
8
Share Link: 
