LTC1693-5 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1693-5' PDF : 8 Pages View PDF
LTC1693-5
APPLICATIONS INFORMATION
Overview
The LTC1693-5 single driver allows 3V- or 5V-based digi-
tal circuits to drive power P-channel MOSFETs at high
speeds. A power MOSFET’s gate-charge loss increases with
switching frequency and transition time. The LTC1693-5
is capable of driving a 1nF load with 16ns rise and fall times
using a VCC of 12V. This eliminates the need for higher
voltage supplies, such as 18V, to reduce the gate charge
losses.
The LTC1693-5’s 360µA quiescent current is an order of
magnitude lower than most other drivers/buffers. This
improves system efficiency in both standby and switching
operation. Since a power MOSFET generally accounts for
the majority of power loss in a converter, addition of the
LT1693-5 to a high power converter design greatly im-
proves efficiency, using very little board space.
Input Stage
The LTC1693-5 employs 3V CMOS compatible input thresh-
olds that allow a low voltage digital signal to drive standard
power P-channel MOSFETs. The LTC1693-5 incorporates
a 4V internal regulator to bias the input buffer. This allows
the 3V CMOS compatible input thresholds (VIH = 2.6V, VIL
= 1.4V) to be independent of variations in VCC. The 1.2V
hysteresis between VIH and VIL eliminates false triggering
due to ground noise during switching transitions. The
LTC1693-5’s input buffer has a high input impedance and
draws less than 10µA during standby.
Output Stage
The LTC1693-5’s output stage is essentially a CMOS
inverter, as shown by the P- and N-channel MOSFETs in
Figure 1 (P1 and N1). The CMOS inverter swings rail-to-
rail, giving maximum voltage drive to the load. This large
voltage swing is important in driving external power
P-channel MOSFETs, whose RDS(ON) is inversely propor-
tional to its gate overdrive voltage (VGS – VT).
The LTC1693-5’s peak output currents are 1.4A (P1) and
1.7A (N1) respectively. The N-channel MOSFET (N1) has
higher current drive capability so it can charge the power
MOSFET’s gate capacitance during high-to-low signal
transitions. When the power MOSFET’s gate is pulled high
by the LTC1693-5, its drain voltage is pulled low by its load
(e.g., a resistor or inductor). The slew rate of the drain
voltage causes current to flow back to the MOSFETs gate
through its gate-to-drain capacitance. If the MOSFET
driver does not have sufficient source current capability
(low output impedance), the current through the power
MOSFET’s Miller capacitance (CGD) can momentarily pull
the gate low, turning the MOSFET back on.
Rise/Fall Time
Since the power MOSFET generally accounts for the ma-
jority of power lost in a converter, it’s important to quickly
turn it either fully “on” or “off” thereby minimizing the tran-
sition time in its linear region. The LTC1693-5 has rise and
fall times on the order of 16ns, delivering about 1.4A to 1.7A
of peak current to a 1nF load with a VCC of only 12V.
The LTC1693-5 rise and fall times are determined by the
peak current capabilities of P1 and N1. The predriver,
shown in Figure 1 driving P1 and N1, uses an adaptive
method to minimize cross-conduction currents. This is
done with a 6ns nonoverlapping transition time. N1 is fully
turned off before P1 is turned-on and vice-versa using this
6ns buffer time. This minimizes any cross-conduction
currents while N1 and P1 are switching on and off yet is
short enough to not prolong their rise and fall times.
VCC
LTC1693-5
P1
OUT
N1
GND
CGS
POWER
MOSFET
CGD
LOAD
1693-5 F01
Figure 1. Capacitance Seen by OUT During Switching
6
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