LTC1709 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC1709
Linear Technology
'LTC1709' PDF : 28 Pages View PDF
LTC1709
APPLICATIO S I FOR ATIO
The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
RDS(ON) = 0.013Ω, CRSS = 300pF. At maximum input
voltage with Tj (estimated) = 110°C at an elevated ambient
temperature:
[ ] PMAIN
=
1.8V
5.5V
(10)2
1+
(0.005)(110°C
−
25°C )
0.013Ω + 1.7(5.5V)2(10A)(300pF)
(300kHz)= 0.65W
The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
( ) ( )( ) PSYNC
=
5.5V − 1.8V
5.5V
2
10A 1.48
0.013Ω
= 1.29W
A short-circuit to ground will result in a folded back current
of about:
ISC
=
25mV
0.004Ω
+
1
2
200ns(5.5V)
1.5µH
=
7A
The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi-
ent temperature and estimated 50°C junction temperature
rise is:
PSYNC
=
5.5V − 1.8V
5.5V
(7A)2 (1.48)(0.013Ω)
= 630mW
which is less than half of the normal, full-load conditions.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.
The duty factor for this application is:
D.F. = VO = 1.8V = 0.36
VIN 5V
Using Figure 4, the RMS ripple current will be:
IINRMS = (20A)(0.23) = 4.6ARMS
An input capacitor(s) with a 4.6ARMS ripple current rating
is required.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure␣ 3 along
with the calculated duty factor. The output ripple in con-
tinuous mode will be highest at the maximum input
voltage since the duty factor is < 50%. The maximum
output current ripple is:
∆ICOUT
=
VOUT
fL
(0.3)
at
33%D. F.
∆ICOUTMAX
=
1.8V
(300kHz)(1.5µH)
0.3
= 1.2ARMS
( ) VOUTRIPPLE = 20mΩ 1.2ARMS = 24mVRMS
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1709. These items are also illustrated graphically in
the layout diagram of Figure␣ 11. Check the following in
your layout:
1) Are the signal and power grounds segregated? The
LTC1709 signal ground pin should return to the (–) plate
of COUT separately. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of CIN, which should have
as short lead lengths as possible.
2) Does the LTC1709 VOS+ pin connect to the point of
load? Does the LTC1709 VOS– pin connect to the load
return?
23
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