LTC1735-1 View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC1735-1

High Efficiency Synchronous Step-Down Switching Regulator

Linear Technology 

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LTC1735-1

APPLICATIO S I FOR ATIO

decreases the output voltage starts at a level lower than

nominal so the output voltage can have more overshoot

and stay within the specified voltage range. Less output

capacitance is required when voltage positioning is used

because more voltage variation is allowed on the output

capacitors.

Active voltage positioning can be implemented using the

OPTI-LOOP architecture of the LTC1735-1 and two resis-

tors connected to the ITH pin. An input voltage offset is

introduced when the error amplifier has to drive a resistive

load. This offset voltage is limited to ±30mV at the input

of the error amplifier. The resulting change in output

voltage is the product of input offset voltage and the

feedback voltage divider ratio.

Figure 8 shows a CPU-core-voltage regulator with active

voltage positioning. Resistors R1 and R5 force the input

voltage offset that adjusts the output voltage according to

the load current level. To select values for R1 and R5, first

determine the amount of output deregulation allowed. The

actual specification for a typical microprocessor allows

the output to vary ±0.112V. The LTC1735-1 reference

R1 PGOOD

27k

C1

39pF

C2

0.1µF

C3

R2 100pF

100k

C4

100pF

R3 680k

R4 100k

R5 100k

1

COSC

16

TG

2

15

RUN/SS BOOST

3

ITH

14

SW

U1

4

LTC1735-1

13

PGOOD

VIN

C7

0.1µF

C8

0.22µF

D1

CMDSH-3

C6

47pF

C5

1000pF

5 SENSE –

12

INTVCC

6 SENSE+

11

BG

7

VOSENSE

10

PGND

C9 +

1µF

C10

4.7µF

10V

8

SGND

9

EXTVCC

5V (OPTIONAL)

accuracy is ±1%. Using 1% tolerance resistors, the total

feedback divider accuracy is about 1% because both

feedback resistors are close to the same value. The result-

ing setpoint accuracy is ±2% so the output transient

voltage cannot exceed ±0.082V. For VOUT = 1.5V, the

maximum output voltage change controlled by the ITH pin

would be:

∆VOSENSE

=

Input

Offset Voltage

VREF

•

VOUT

= ± 0.03V • 1.5 = ±56mV

0.8V

With optimum resistor values at the ITH pin, the output

voltage will swing from 1.55V at minimum load to 1.44V

at full load. At this output voltage, active voltage position-

ing provides an additional ±56mV to the allowable tran-

sient voltage on the output capacitors, a 68% improvement

over the ±82mV allowed without active voltage

positioning.

Q1

FDS6680A

C9, C19: TAIYO YUDEN JMK107BJ105

C10: KEMET T494A475M010AS

C12 TO C14: TAIYO YUDEN GMK325F106

C15 TO C18: PANASONIC EEFUE0G181R

D1: CENTRAL SEMI CMDSH-3

D2: MOTOROLA MBRS340

L1: PANASONIC ETQP6F1R0SA

Q1 TO Q3: FAIRCHILD FDS6680A

R5: IRC LRF2512-01-R003-J

U1: LINEAR TECHNOLOGY LTC1735CS-1

C12 TO C14

10µF

35V

VIN

7.5V TO

24V

GND

D2

MBRS340

Q2, Q3

FDS6680A

×2

L1

R6

1µH 0.003Ω

C11

330pF

R7

10k

+

R8

11.5k

C15 TO

C18

180µF

4V

VOUT

1.5V

15A

C19

1µF

GND

1735-1 F08

Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning

21

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