LTC1741 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1741' PDF : 20 Pages View PDF
LTC1741
APPLICATIO S I FOR ATIO
An analog ground plane separate from the digital process-
ing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC VDD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1741 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should con-
nect to the digital processing system ground. The output
driver supply, OVDD should be connected to the digital
processing system supply. OVDD bypass capacitors should
bypass to the digital system ground. The digital process-
ing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1741 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside envi-
ronment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evalu-
ation circuit shown on the following pages has a low ther-
mal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35°C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
1741f
17
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