LTC1741IFW View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC1741IFW

12-Bit, 65Msps Low Noise ADC

Linear Technology 

1 2 3 4 5 6 7 8 9 10 Next

BLOCK DIAGRA

LTC1741

AIN+

INPUT

AIN–

S/H

VCM

4.7µF

2.35V

REFERENCE

RANGE

SELECT

REF

SENSE

BUF

FIRST PIPELINED

ADC STAGE

(5 BITS)

DIFF

REF

AMP

SECOND PIPELINED

ADC STAGE

(4 BITS)

THIRD PIPELINED

ADC STAGE

(4 BITS)

REFL

REFH INTERNAL CLOCK SIGNALS

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

CONTROL LOGIC

AND

CALIBRATION LOGIC

WU

W

TI I G DIAGRA

REFLB REFHA REFLA REFHB ENC ENC

4.7µF

0.1µF

1µF

0.1µF

1µF

MSBINV

OE

Figure 1. Functional Block Diagram

FOURTH PIPELINED

ADC STAGE

(2 BITS)

SHIFT REGISTER

AND CORRECTION

OUTPUT

DRIVERS

OVDD 0.5V TO

5V

OF

D11

D0

CLKOUT

OGND

1741 F01

ANALOG

INPUT

N•

t3

ENC

t7

DATA

t6

CLKOUT

t4

OE

t11

DATA

t1

t2

t8

DATA (N – 5)

DB11 TO DB0

t5

t12

DATA N

DB11 TO DB0, OF AND CLKOUT

t0

DATA (N – 4)

DB11 TO DB0

DATA (N – 3)

t10

t9

1741 TD

1741f

9

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