LTC1746 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1746' PDF : 20 Pages View PDF
LTC1746
APPLICATIO S I FOR ATIO
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1746 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100Ω or less for each input. The S/H
circuit is optimized for a 50Ω source impedance. If the
source impedance is less than 50Ω, a series resistor
should be added to increase this impedance to 50Ω. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1746 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100Ω for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
The 25Ω resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 50MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
ANALOG
INPUT
0.1µF
100Ω
VCM
4.7µF
1:1
25Ω
12pF
25Ω AIN+
LTC1746
100Ω
25Ω
12pF
25Ω AIN–
12pF
1746 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
SINGLE-ENDED
INPUT
2.35V ±1/2
RANGE
5V
+
1/2 LT1810
–
100Ω
500Ω
+
1/2 LT1810
–
500Ω
VCM
4.7µF
12pF
25Ω
25Ω AIN+
LTC1746
12pF
25Ω
25Ω AIN–
12pF
1746 F04
Figure 4. Differential Drive with Op Amps
1746f
13
Share Link: 
