LTC1850/LTC1851
PI FU CTIO S
PIN
1 to 8
9
10
11
12
13
14
15
16
17
18
19
20
21
21
22
22
23
23
24 to 30
24 to 32
31 to 32
33
34
35
36
37
38
39 to 41
42
43
44
45
46
47
48
NAME
CH0 to CH7
COM
REFOUT
REFIN
REFCOMP
GND
VDD
VDD
GND
DIFFOUT/S6
A2OUT/S5
A1OUT/S4
A0OUT/S3
D9/S2 (LTC1850)
D11/S2 (LTC1851)
D8/S1 (LTC1850)
D10/S1 (LTC1851)
D7/S0 (LTC1850)
D9/S0 (LTC1851)
D6 to D0 (LTC1850)
D8 to D0 (LTC1851)
NC (LTC1850)
BUSY
OGND
OVDD
M0
PGA
UNI/BIP
A0 to A2
DIFF
WR
RD
CONVST
CS
SHDN
M1
DESCRIPTION
Analog Inputs
Analog Input Common Pin
2.5V Reference Output
Reference Buffer Input
Reference Buffer Output
Ground, Substrate Ground
Supply
Supply
Ground
Single-Ended/Differential Output
MUX Address Output
MUX Address Output
MUX Address Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Outputs
Data Outputs
Converter Busy Output
Output Ground
Output Supply
Mode Select Pin 0
Gain Select Input
Unipolar/Bipolar Input
MUX Address Inputs
Single-Ended/Differential Input
Write Input, Active Low
Read Input, Active Low
Conversion Start Input, Active Low
Chip Select Input, Active Low
Shutdown Input, Active Low
Mode Select Pin 1
MIN
0
0
0
4.75
4.75
OGND
OGND
OGND
OGND
OGND
OGND
OGND
OGND
OGND
OGND
OGND
OGND
NOMINAL (V)
TYP
2.5
2.5
4.096
0
5
5
0
MAX
VDD
VDD
VDD
5.25
5.25
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
ABSOLUTE MAXIMUM (V)
MIN
MAX
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
6
– 0.3
6
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
OGND
0
2.7
5
0
0
0
0
0
0
0
0
0
0
0
OVDD
5.25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
– 0.3
6
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
– 0.3
10
18501f
12