LTC1860 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1860' PDF : 16 Pages View PDF
LTC1860/LTC1861
APPLICATIONS INFORMATION
CONV
SDI
tCONV
SLEEP MODE
DON’T CARE
SCK
tSMPL
S/D O/S
DON’T CARE
1 2 3 4 5 6 7 8 9 10 11 12
SDO
Hi-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1860 F04
Figure 4. LTC1861 Operating Sequence
111111111111
111111111110
•
•
•
000000000001
000000000000
*VIN = (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
Figure 5. LTC1861 Transfer Curve
VIN*
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
1860 F05
MUX MODE
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SGL/DIFF ODD/SIGN
1
0
1
1
0
0
0
1
CHANNEL #
0
1
+
+
+
–
–
+
GND
–
–
186465 TBL1
LTC1861 OPERATION
Operating Sequence
The LTC1861 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV, the conversion is
finished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being trans-
mitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems.
The data is transmitted and received simultaneously (full
duplex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefinitely. See Figure 4.
12
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND (or AGND). A zero code will occur when
the “+” input minus the “–” input equals zero. Full scale
occurs when the “+” input minus the “–” input equals
VREF minus 1LSB. See Figure 5. Both the “+” and “–”
inputs are sampled at the same time so common mode
noise is rejected. The input span in the SO-8 package is
fixed at VREF = VCC. If the “–” input in differential mode
is grounded, a rail-to-rail input span will result on the
“+” input.
18601fa
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